1. Field of the Invention
This invention relates to processors. More specifically, this invention relates to processors implementing a system management mode of operation.
2. Description of the Related Art
System management mode (SMM) is a processor operating mode for performing high level systems functions such as power management or security functions.
Different microprocessor manufacturers have implemented SMM systems differently so that some SMM functionality is standard or semi-standard and other functionality is very different. A primary constant feature in different SMM implementations is that the high level functions operating under SMM, and the underlying SMM operations, are transparent both to operating systems and application software. Another common characteristic of various SMM implementations is that SMM functionality is hardcoded into the processor integrated circuit chip and, thus, is permanently fixed.
One problem with the conventional, hardcoded SMM implementation is that differences in SMM implementations by various processor manufacturers give rise to incompatibilities in functionality for processor chips that are otherwise designed for compatibility. A second problem is that the hardcoded SMM implementation may be highly advantageous for some applications, but disadvantageous for other applications. For example, a full-functionality but high overhead SMM implementation may be desired in some applications while a reduced-functionality, low overhead implementation is better suited in other applications. Another problem is that some computer system integrators wish to implement special-purpose or proprietary SMM functionality.
In accordance with the present invention, a system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is xe2x80x9csoftxe2x80x9d and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.
An embodiment of a RISC superscalar processor having a conventional hardwired system management mode (SMM) functionality, including SMM entry and exit processing and other nonconventional x86 instructions that support SMM software, is implemented in on-chip ROM resident RISC operation sequences. This hardwired implementation of SMM requires exact definition of SMM functionality to satisfy system requirements for multiple various vendors of computer systems which incorporate the RISC superscalar processor. An embodiment of a RISC superscalar processor in accordance with the present invention instead fetches SMM RISC operation sequences, when needed, from an external memory. In one embodiment, the SMM RISC operation sequences are stored in an area of address space where system BIOS resides (addresses E0000-FFFFF). As a result, each system vendor of multiple vendors can freely define much of the SMM functionality exactly as desired. For example, SMM entry and the associated state saving performed by the processor can be streamlined or extended, as desired.
In accordance with the present invention, system management mode is a xe2x80x9csoftxe2x80x9d implementation, having a definition in external RISC instruction code residing within BIOS. In this soft implementation, nearly all aspects of SMM are freely defined. A separate SMM entry slot is reserved for each SMM entry mechanism. Exit from SMM is furnished by a special xe2x80x9cSMM exitxe2x80x9d instruction. trap filtering and checking are also defined. Furthermore, additional x86 SMM support instructions are defined, including instructions to save and restore segment descriptors.
In accordance with a first embodiment of the present invention, a computer system for operating in a system management mode (SMM) includes a processor having an instruction decoder, means connected to the processor for activating a system management activation signal and an instruction memory connected to the processor for supplying instructions to the processor. The instruction memory stores a software program including an SMM initialization routine, a routine for redirecting SMM operations to an external memory and an SMM termination routine.
In accordance with a second embodiment of the present invention, a computer system includes a processor and a memory connected to the processor. The memory includes a BIOS area of memory address space. A method of operating a computer system in a system management mode (SMM) includes the steps of receiving an SMM activating signal, recognizing the received SMM activating signal, initializing a SMM entry sequence by vectoring to a RISC instruction in a BIOS area of the memory address space, initializing the SMM, redirecting SMM operations to an external memory and terminating the SMM.
Several advantages are achieved by the described invention. One advantage is that the system management mode (SMM) operation is transparent to the operation of all other software so that other software operates identically whether SMM is active or inactive. Similarly, SMM operation is transparent to the operation of all normal CPU operating modes. Another advantage is that the functional definition of SMM is fully-defined, and therefore modifiable, by operating software. These advantages are attained while system management interrupts (SMI) and I/O access trapping are fully supported and SMM may be implemented to be compatible with conventional SMM operation.